3d7424 monolithic quad 4-bit programmable delay line (series 3d7424) features ? four indep?t programmable lines on a single chip ? all-silicon cmos technology ? low quiescent current (5ma typical) ? leading- and trailing-edge accuracy ? vapor phase, ir and wave solderable ? increment range: 0.75ns through 400ns ? delay tolerance: 3% or 2ns (see table 1) ? line-to-line matching: 1% or 1ns typical ? temperature stability : 1.5% typical (-40c to 85c) ? vdd stability : 0.5% typical (4.75v to 5.25v) ? minimum input pulse w i dth: 10% of total delay functional description the 3d7424 device is a small, versatile, quad 4-bit programmable monolithic delay line. delay values, pr ogrammed via the serial interface, can be independently varied over 15 equal steps. the step size (in ns) is determined by the device dash number. each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. for each line, the delay time is given by: td n = t0 + a n * ti where t0 is the inherent delay, a n is the delay address of the n-th line and ti is the delay increment (dash number). the desired addresses are shifted into the device via the sc and si inputs, and the addresses are latched using the al input. the serial interface can also be used to enable/disabl e each delay line. the 3d7424 operates at 5 volts and has a typical t0 of 6ns. the 3d7424 is ttl/cmos-com patible, capable of sourcing or sinking 4ma loads, and features both rising- and falling-edge accuracy. the device is offered in a standard 14-pin auto- insertable dip and a space saving surface mount 14-pin soic. packages 14 13 12 11 10 9 8 1 2 3 4 5 6 7 i1 sc i2 i3 i4 si gnd vdd a l o1 so o2 o3 o4 dip - 14 3 d 74 24 -x x 1 2 3 4 5 6 7 14 13 12 11 10 9 8 i1 sc i2 i3 i4 si gn d vd d a l o1 so o2 o3 o4 so i c - 1 4 3d 7424d- x x pin descriptions i1-i4 signal inputs o1-o4 signal outputs al address latch in sc serial cloc k in si serial data in so serial data out vdd 5.0v gnd ground f o r mechanical dimensions, click here . f o r package marking details, click here . table 1: part number specifications dela ys & tolera nces (ns) i n put restri cti o ns m ax fr equency m i n pul se wi dth part number del a y step i nher e nt del a y total del a y rel a ti ve tolerance r e c o m ? d a b s o l u t e r e c o m ? d a b s o l u t e 3d7424-.75 .75 0.19 6.0 2.0 17.25 2.0 3% or 0.50ns 19 mhz 166 mhz 26 ns 3.0 ns 3d7424-1 1.0 0.25 6.0 2.0 21.0 2.0 3% or 0.50ns 16 mhz 166 mhz 32 ns 3.0 ns 3d7424-1.5 1.5 0.38 6.0 2.0 28.5 2.0 3% or 0.50ns 12 mhz 111 mhz 43 ns 4.5 ns 3d7424-2 2.0 0.50 6.0 2.0 36.0 2.0 3% or 0.75ns 9.2 mhz 83 mhz 54 ns 6.0 ns 3d7424-4 4.0 1.00 6.0 2.0 66.0 2.0 3% or 0.75ns 5.0 mhz 83 mhz 99 ns 6.0 ns 3d7424-5 5.0 1.25 6.0 2.0 81.0 2.5 3% or 0.75ns 4.1 mhz 66 mhz 122 ns 7.5 ns 3d7424-10 10 2.50 6.0 2.0 156 5.0 3% or 1.25ns 2.1 mhz 33 mhz 234 ns 15.0 ns 3d7424-15 15 3.75 6.0 2.0 231 7.5 3% or 1.88ns 1.4 mhz 22 mhz 347 ns 22.5 ns 3d7424-20 20 5.00 6.0 2.0 306 10 3% or 2.50ns 1.0 mhz 16 mhz 459 ns 30.0 ns 3d7424-40 40 10.0 6.0 2.0 606 20 3% or 5.00ns 550 khz 8.3 mhz 909 ns 60.0 ns 3d7424-50 50 10.0 6.0 2.0 756 25 3% or 6.25ns 440 khz 6.6 mhz 1.2 us 75.0 ns 3d7424-100 100 12.5 6.0 2.0 1506 50 3% or 12.5ns 220 khz 3.3 mhz 2.3 us 150 ns 3d7424-200 200 20.0 6.0 2.0 3006 100 3% or 25.0ns 110 khz 1.6 mhz 4.5 us 300 ns 3d7424-400 400 40.0 6.0 2.0 6006 200 3% or 50.0ns 55 khz 833 khz 9.0 us 600 ns note: a n y increment betw een 0.75ns and 400ns not show n is also av ailable as standard see page 4 for details regarding input restrictions ? 2006 data delay dev i ces doc #06019 data delay devices, inc. 1 6/5/2006 3 mt. prospect ave. clifton, nj 07013
3d7424 application notes theory of operation programmed delay interface the quad 4-bit programmable 3d7424 device architecture is comprised of four independently operating delay lines. each delay line produces at its output a replica of the signal present at its input, shifted in time. a single delay line is comprised of a number of delay cells connected in series. delay selection is achieved by routing one output in each string of cells to its respective output pin (o1-o4). the del ay of each of the four lines can be controlled independently, via the serial interface, as described in the next section. figure 1 illustrates the main functional blocks of the 3d7424 device. since the device is a cmos design, all unused input pins must be returned to well defined logic levels (vdd or gnd). the delays are adjusted by first shifting a 20-bit programming word into the device via the sc and si pins, then strobing the al signal to latch the values. the bit sequence is shown in table 2, and the associated timing diagram is shown in figure 2. each line has associated with it an enable bit. setting this bit low will force the corresponding delay line output to a high impedance state, while setting it high returns the the change in delay from one address setting to the next is called the increm ent , or lsb. it is nominally equal to the device dash number. the minimum delay, achieved by setting the address of a line to zero, is called the inherent delay . line to its normal operation. the device contains an so output, which can be used to cascade multiple devices, as shown in figure 3. table 2: bit sequence for best performance, it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. also, signal traces should be kept as short as possible. b i t d e l a y line function 1 4 output e n a b l e 2 3 output e n a b l e 3 2 output e n a b l e 4 1 output e n a b l e 5 address bit 3 6 address bit 2 7 address bit 1 8 1 address bit 0 9 address bit 3 10 address bit 2 11 address bit 1 12 2 address bit 0 13 address bit 3 14 address bit 2 15 address bit 1 16 3 address bit 0 17 address bit 3 18 address bit 2 19 address bit 1 20 4 address bit 0 de l a y li n e 20 - b i t la t ch 2 0 - bit sh if t re g i st e r so figure 1: functional block diagr a m del a y li ne d e l ay li ne de la y li ne i4 i3 i2 i1 o4 o3 o2 o1 a l si sc en ab l es addr4 a d dr3 a ddr 2 a ddr1 new val u es new bi t 1 ne w bi t 20 ne w bi t 2 ol d bi t 1 ol d bi t 2 ol d bi t 20 la t c h (al) cl o c k (sc ) seri a l in p u t ( si ) seri a l out p ut ( so ) del a y ti m e s t lw t cw t cw t cs l t ds c t dh c t pc q t ld v t ld x previ o u s val ues fig u r e 2 : s e r i a l inte r f a c e tim i n g dia g r a m ne w bi t 1 doc #06019 data delay devices, inc. 2 6/5/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7424 application notes (cont?d) delay accuracy there are a number of ways of characterizing the delay accuracy of a programmable line. the first is the differential nonlinearity (dnl), also referred to as the increment error. it is defined as the deviation of the delay step at a given address from its nominal value. for all dash numbers, the dnl is within 1/4 lsb at every address (see table 1: delay step). the integrated nonlinearity (inl) is determined by first constructing t he least-squares best fit straight line through the delay-versus-address data. the inl is then the deviation of a given delay from this line. for all dash numbers, the inl is within 1.0 lsb at every address. the relative error is defined as follows: e rel = (t i ? t 0 ) ? i * t inc where i is the address, t i is the measured delay at the i?th address, t 0 is the measured inherent delay, and t inc is the nominal increment. it is very similar to the inl, but simpler to calculate. for most dash numbers, the relative error is less than 1/8 lsb at every address (see table 1: relative tolerance). the absolute error is defined as follows: e abs = t i ? (t inh + i * t inc ) where t inh is the nominal inherent delay. the absolute error tolerance is given for addresses 0 and 15 (see table 1: inherent delay, total delay, respectively). at any intermediate address, the tolerance can be found via linear interpolation of the address 0 & address 15 tolerances. the m a tching error is a measure of how well the delay of the four lines track each other when they are all programmed to the same address. the lines are typically matched to within 1% or 1ns, whichever is greater, for all addresses and all dash numbers. delay stability the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the 3d7424 utilizes novel compensation circuitry to minimize the delay variations induced by fluctuations in power s upply and/or temperature. with regard to stability, the delay of the 3d7424 at a given address, i, can be split into two components: the inherent delay (t 0 ) and the relative delay (t i ? t 0 ). these components exhibit very different stability coefficients, both of which must be considered in very critical applications. the thermal coefficient of the relative delay is limited to 250 ppm/c, which is equivalent to a variation, over the -40c to 85c operating range, of 1.5% from the room-temperature delay settings. this holds for dash numbers greater than 1. for smaller dash numbers, the thermal drift will be larger and will always be positive. the thermal coefficient of the inherent delay is nominally +15ps/c for all dash numbers. the power supply sensitivity of the relative delay is 0.5% over the 4.75v to 5.25v operating range, with respect to the delay settings at the nominal 5.0v power supply. this holds for all dash numbers greater than 1. for smaller dash numbers, the voltage sensitivity will be greater and will always be negative. the sensitivity of the inherent delay is nominally -1ps/mv for all dash numbers. from w r it ing device to nex t device si so sc a l 3d7424 3d7424 3d7424 f i g u r e 3: cascad in g m u lt ip le dev i ces si so sc a l si so sc a l doc #06019 data delay devices, inc. 3 6/5/2006 3 mt. prospect ave. clifton, nj 07013
3d7424 application notes (cont?d) input signal considerations the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore, a recommended and an absolute maximum operating input frequency and a recommended and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the recommended maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. operation above the recommended maximum frequency will cause the delays to shift slighty with respect to their values at low-frequency operation. the magnitudes of these deviations will increase as the absolute maximum frequency is approached. however, if the input frequency and pulse width remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1, determines the smallest pul se width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines t he smallest pulse width of the delay line input si gnal for which the output delay accuracy tabulated in table 1 is guaranteed. operation below the recommended minimum pulse width will cause the delays to shift slighty with respect to their values at long-pulse-width operation. the magnitudes of these deviations will increase as the absolute minimum pulse width is approached. however, if the input pulse width and frequency remain constant, the device will exhibit the same delays from one period to the next (ie, no appreciable jitter). programmed delay update a delay line is a memory device. it stores information present at the input for a time equal to the delay setting before presenting it at the output. each 4-bit delay line in the 3d7424 is represented by 15 serially connected delay elements (individually addressed by the programming data), each capable of storing data for a time equal to the device increment (step time). the delay line memory property, in conjunction with the operational requirement of ?instantaneously? connecti ng the delay element addressed by the programming data to the output, may inject spurious information onto the output data stream. in order to ensure that spurious outputs do not occur, it is essential that the input signal be idle (held high or low) for a short duration prior to updating the programmed delay. this duration is given by the maximum programmable delay. satisfying this requirement allows the delay line to ?clear? itself of spurious edges. once the new address is loaded, the input signal can begin to switch. doc #06019 data delay devices, inc. 4 6/5/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7424 doc #06019 data delay devices, inc. 5 6/5/2006 3 mt. prospect ave. clifton, nj 07013 device specifications table 3: absolute maximum ratings parameter symbol min max units notes dc supply voltage v dd -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v input pin current i in -10 10 ma 25c storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 4: dc electrical characteristics (-40c to 85c, 4.75v to 5.25v) parameter symbol min typ max units notes static supply current* i dd 5.0 7.0 ma v dd = 5.25v high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level input current i ih -0.1 0.0 0.1 p a v ih = v dd low level input current i il -0.1 0.0 0.1 p a v il = 0v high level output current i oh -8.0 -6.0 ma v dd = 4.75v v oh = 2.4v low level output current i ol 6.0 7.5 ma v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 ns c ld = 5 pf *i dd (dynamic) = 4 * c ld * v dd * f input capacitance = 10 pf typical where: c ld = average capacitance load/line (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) table 5: ac electrical characteristics (-40c to 85c, 4.75v to 5.25v) parameter symbol min typ max units notes latch width t lw 10 ns data setup to clock t dsc 10 ns data hold from clock t dhc 1 ns clock width (high or low) t cw 15 ns clock setup to latch t csl 20 ns clock to serial output t pcq 12 20 ns latch to delay valid t ldv 35 45 ns 1 latch to delay invalid t ldx 5 ns 1 input pulse width t wi 10 % of total delay see table 1 input period period 20 % of total delay see table 1 input to output delay t plh , t phl ns see text notes: 1 - refer to programmed delay update section
3d7424 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vdd): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.3v 0.1v threshold: 1.65v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.7v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out1 out2 out4 out3 out tr i g in ref tr i g fi gu r e 4 : t e st s e tu p dev i ce un de r t e st ( dut ) di g i t a l sco p e/ t i m e i n t e rva l co unt er pu l s e ge ne ra t o r in 4 co m p ut er sy st em pr i n t e r in 3 in 2 in 1 figur e 5 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 65v 1. 65v 2. 7v 2. 7v 1. 65v 1. 65v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #06019 data delay devices, inc. 6 6/5/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
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